Various techniques related to a charge/discharge protection circuit of a lithium-ion secondary battery have been proposed. For example, Japanese Laid-Open Patent Publication No. 2002-176730 discloses a semiconductor device employed as a protection circuit of a battery pack as is shown in FIG. 5.
The illustrated semiconductor device (charge/discharge protection circuit) 1 as a main component of a battery pack A includes an overcharge detection circuit 11, an over-discharge detection circuit 12, a discharge over-current detection circuit 13, a short-circuit detection circuit 14, an oscillation circuit 16, a counter circuit 17, logic circuits 18, 20, a level shift circuit 19, a charge over-current detection circuit 21, delay circuits 24, 25, and a delay time reduction circuit 23.
In the following, basic operations performed by the semiconductor device (charge/discharge protection circuit) 1 are described.
When overcharge, over-discharge, discharge over-current, charge over-current, or short-circuit is detected by the overcharge detection circuit 11, the over-discharge detection circuit 12, the discharge over-current detection circuit 13, the charge over-current detection circuit 21, or the short-circuit detection circuit 14, the oscillation circuit 16 is activated and the counter circuit 17 starts counting operations.
After the counter circuit 17 counts to a predetermined detection delay time that is set for a corresponding detection, in the case of overcharge or charge over-current detection, a Cout output is switched to low level “L” via the logic circuit (e.g., latch circuit) 18 and the level shift circuit 19 so that a charge control FET Q1 is turned off; and in the case of over-discharge, discharge over-current, or short-circuit detection, a Dout output is switched to low level “L” via the logic circuit 20 so that a discharge control FET Q2 is turned off.
When a charger is connected to the battery pack A so that charge current flows into the battery pack A, the source voltage of the charge control FET Q1 becomes lower than the source voltage of the discharge control FET Q2. It is noted that the source voltage of the discharge control FET Q2 corresponds to the Vss terminal voltage of the semiconductor device 1, and although a resistance is connected to a V− terminal of the semiconductor device, since the V− terminal has high impedance, the source voltage of the charge control FET Q1 may be substantially equal to the V− terminal voltage of the semiconductor device 1.
Accordingly, when charge current is supplied, the V− terminal voltage becomes lower than the Vss terminal voltage. When the difference between the V− terminal voltage and the Vss terminal voltage reaches a predetermined voltage (charge over-current detection voltage), charge over-current is detected so that the output of terminal Cout is switched to low level “L” and the charge control FET Q1 is turned off. It is noted that the relationship between a charge over-current value I, a charge over-current detection voltage Vchgdet, the ON resistance Ron1 of the charge control FET Q1, and the ON resistance Ron2 of the discharge control FET Q2 may be expressed by the following formula:I=Vchgdet/(Ron1+Ron2)
The above-described operations are basic operations performed by the charge/discharge protection circuit (semiconductor device) of FIG. 5 upon detecting overcharge, over-discharge, charge over-current, discharge over-current, or short-circuit.
In the following, the function and circuit configuration of the delay time reduction circuit 23 are briefly described.
Normally, the delay time set with respect to overcharge detection by the overcharge detection circuit 11 is at least 1 second so that a test time for testing the semiconductor device 1 may be relatively long.
In turn, when testing the semiconductor device 1 or a protection circuit substrate, a TEST terminal may be set to low level “L” so that the output frequency of the oscillation circuit 16 may be increased and the detection delay time may be decreased to enable reduction of the test time. It is noted that this scheme may also be applied to overcharge, over-discharge, or discharge over-current detection but is particularly advantageous when applied to overcharge detection that requires a relatively long delay time.
The oscillation circuit 16 may be a ring oscillator that includes a constant current inverter and a condenser, for example. It is noted that the oscillation frequency of a ring oscillator is determined by a constant current value of a constant current source, a capacitor value, and a threshold value of the constant current inverter. Thus, a method for reducing the delay time may involve setting the signal of the test terminal to low level “L” to thereby (a) increase the constant current value of the constant current source; (b) substantially decrease the capacity value of a capacitor; or (c) change the threshold value of the constant current inverter of the ring oscillator, for example.
In another example, the position at which the output of the counter circuit 17 is obtained may be changed to reduce the delay time instead of changing the oscillation frequency of the oscillation circuit 16, the details of which are described in Japanese Laid-Open Patent Publication No. 2002-176730.
In the charge/discharge protection circuit shown in FIG. 5, recovery from over-discharge status to dischargeable status may be realized by establishing connection with a charger. In this case, if a Vdd terminal voltage is less than or equal to an over-discharge detection voltage when a charger is connected, a charge current is supplied via a parasitic diode of the discharge control FET Q2, and then, after the Vdd terminal voltage becomes higher than the over-discharge detection voltage, the output of terminal Dout may be set to high level “H” to turn on the discharge control FET Q2 and switch to dischargeable status. On the other hand, if the Vdd terminal voltage is higher than the over-discharge detection voltage when the charger is connected, the Dout terminal may be immediately switched to high level “H”.
It is noted that a PIN for recognizing charger connection or a comparator may be used to enable such charger connection recovery operations. However, the number of terminals has to be increased at the charger side as well as the IC side when the PIN is used, and in the case where the comparator is used, the chip size has to be increased so that current consumption may be increased.
Accordingly, there is a demand for a charge/discharge protection circuit that is capable of controlling on/off operations of a discharge control FET using existing PINs and circuits, preventing the current consumption and the chip size from increasing, preventing degradation of the discharge control FET when a charger is connected, and reducing a battery charge time. There is also a demand for a battery pack embedding such a charge/discharge protection circuit and an electronic apparatus using such a battery pack.